The present invention relates to an improvement in an insulation gate FET, especially for a power insulated gate FET.
An insulated gate FET has a technical advantage of high speed operation in comparison with a general bipolar transistor since it is a majority carrier device. Especially in recent years, the advantage of the insulated gate FET is being recognized, and the insulated gate FET is being improved into a large power type.
FIG. 1 shows a sectional elevation view of the conventional insulated gate FET for high power use. The conventional insulated gate FET device has,as shown in FIG. 1, a high concentration n-type substrate having a (100) plane as its principal face, an epitaxially grown low concentration n-type layer 2 formed on the substrate 1, a p-type diffused layer further grown on the n-type epitaxial layer 2, the diffused p-type layer 3 to become a channel region, high concentration n.sup.+ -type diffused regions 4 to become source regions formed from the surface of the p-type diffused layer, source electrodes 5, gate insulation films 6 and gate electrodes 7.
The gate electrodes are made in a V-shape by utilizing a difference in the etching speed of the (100) plane and the (111) plane, namely anisotropic etching method, carried out from the surface of the substrate wafer. Accordingly the channel regions 3 are formed on (111) plane, accordingly the electron mobility is small, and thereby the channel resistance is large and hence the ON-resistance is large. In order to reduce this ON-resistance, to reduce the thickness of the channel region 3 or to grow the concentration of the channel region 3 can he considered, but such measure results n lowering of breakdown voltage, and therefore the measure has a limit.